Microelectronic devices, such as integrated circuits incorporating metal-oxide-semiconductor transistors (MOSFETs), or the like, continue to scale by reducing pitches between adjacent features and incorporating three-dimensional transistor structures (e.g., finFETs). As transistor density and non-planarity increases, so too does the interconnect metallization, increasing interconnect capacitance and making electrical isolation more difficult. Interconnect processes over the last decade have increasingly incorporated “low-k” films (e.g., those below ˜3.2) as the material of choice of inter-level dielectrics (ILDs), some further implementing air gap formation whereby voids in the ILD between adjacent metal lines are deliberately introduced. Also, topography present due to radical 3D structures may induce voids and/or defects that need to be sealed/covered by a conformal dielectric layer.
Plasma enhanced chemical vapor deposition (PECVD) processes are typically used for dielectric deposition in low-k interconnect applications but do not offer high conformality/step coverage. For example, a PECVD low-k film typically has conformality less than 55% (e.g., only approaching 75% with a dep/etch/dep type sequence) where a dielectric has deposited thickness on vertical (e.g., sidewall) surface that is less than 55% of the deposited thickness on a horizontal (e.g., top) surface. CVD or low pressure CVD (LPCVD) techniques offer higher conformality, but require temperatures higher than typically permissible for low-k interconnect applications.
It is often desirable to provide a hermetic seal with a dielectric layer, for example to prevent out-diffusion of metal (e.g., Cu) from a metal interconnect line into surrounding ILD material, as well as to prevent moisture and wet chemical in-diffusion from surrounding ILD (or from a void in an air gap formation process) into a 3D structure (e.g., metal line, transistor, etc.). Due to difficulties in achieving perfect coverage and film densification over 3D topography, there is therefore a minimum thickness requirement for a dielectric diffusion barrier.
Materials and techniques to reduce a dielectric diffusion barrier minimum thickness are therefore advantageous.